Wireline serial transceivers, such as, for example, serializer/deserializers (SerDess) are ubiquitous in communication networks, as they operate to connect the processing cores of integrated circuits (IC s) with other elements. In so doing, SerDess are configured to perform numerous tasks, including channel equalization, clock and data recovery, serialization and deserialization of the output/input data etc. Further, modern communication ICs may employ a large number of SerDess and clock multiplication units (CMUs), collectively known as “Macros”, on single chips. However, IC designs incorporating a large number of Macros may put certain limits on the effective utilization of spatial areas and power consumption.
Moreover, the operation of the Macros generally require a reference clock, in which the reference clock frequency is converted into a high-speed clock frequency by using a phase lock loop (PLL) in order to enable synchronization with incoming data rate. Typically, this high-speed clock frequency conversion takes place in the CMU that is integrated as a separate unit from various SerDess in order to effectively utilize the available spatial area and power resources. In this configuration, the CMU is capable of supplying the high-speed clock to various SerDess within the Macros.
It will be appreciated that in certain communication networks, the data rates of individual incoming data streams may contain substantial variations, requiring the various SerDess, operating at different high-speed clock rates, to accommodate the incoming data rate variations. To combat these incoming data rate variations, various Macros employ CMUs that are configured to generate and supply different high-speed clock rates to various SerDess by employing multiple distinct busses for different high-speed clock frequency transmissions.
However, the implementation of distinct busses for different high-speed clock frequencies rates typically requires more spatial area for implementation in IC designs, resulting in increased spatial area costs. Similarly, the spatial area costs are further increased by the need to have each of the distinct busses arranged to have a certain degree of isolation from each other. Moreover, the use of multiple busses generally results in increased power consumption that is required to charge corresponding conductors. Thus, the use of distinct, multiple busses presents certain spatial area and power consumption challenges for effective IC designs.